Analog Fault Simulation: Need it? No. It is already done

Analog design requires simulation comprehending detailed and accurate semiconductor process knowledge in order to produce designs which will (one hopes) meet narrowly defined specifications. QED The fault simulation is already done! ((Quod erat demonstrandum = which was to be demonstrated.) for those, like me, wondering what the latin acronym means...) Model-to-hardware correlation is a requirement for design success. The simulation of analog devices occurs in the same manner as digital devices for reasonably small counts of devices. It is only when large numbers of digital devices are connected together that the expedient of switch based stuck fault testing is applied. Is there yet an ‘analog’ to the digital modeling process? Should there be? Simulating gross faults, like stuck fault behavior, using switch based methods is pointless when applied to complex analog circuits. Clearly the simulated defective analog behavior will deviate from the expected unless aliasing is possible. Murphy will ensure its untimely arrival. For combined analog functions ‘logic depth’ grows much more rapidly than digital logic having similar transistor counts, particularly if the combined analog devices have continuous response ranges. What does coverage mean in this environment? How is a passing range of values defined?